Manufacturing method of semiconductor device

ABSTRACT

To manufacture a semiconductor device by a method including the steps of: forming an oxide over a substrate, a first conductor over the oxide, and a second conductor over the first conductor; forming a first insulator to cover the oxide, the first conductor, and the second conductor; forming an opening in the first insulator to divide the second conductor into a third conductor and a fourth conductor; forming a second insulator and a third insulator to cover the oxide and the first insulator; processing the second insulator and the third insulator into a fourth insulator and a fifth insulator; processing the first conductor using the fourth insulator and the fifth insulator as a mask to divide the first conductor into a fifth conductor and a sixth conductor; and removing the fifth insulator.
BACKGROUND OF THE INVENTION 1. Field of the Invention

One embodiment of the present invention relates to a semiconductor device, a storage device, and an electronic device each including an oxide semiconductor. One embodiment of the present invention relates to a method of manufacturing the semiconductor device.
Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention include a semiconductor device, a display device, a light-emitting apparatus, a power storage device, a storage device, an electronic device, a lighting device, an input device (e.g., a touch sensor), an input/output device (e.g., a touch panel), a method of driving any of them, and a method of manufacturing any of them.
 In this specification and the like, a semiconductor device generally means a device that can function by utilizing semiconductor characteristics. A semiconductor element such as a transistor, a semiconductor circuit, an arithmetic device, and a storage device are each an embodiment of the semiconductor device. A display device (e.g., a liquid crystal display device and a light-emitting display device), a projection device, a lighting device, an electro-optical device, a power storage device, a storage device, a semiconductor circuit, an imaging device, an electronic device, and the like may include a semiconductor device.
2. Description of the Related Art

In recent years, semiconductor devices have been developed to be used mainly for an LSI, a CPU, a memory, and the like. A CPU is an aggregation of semiconductor elements; the CPU includes a semiconductor integrated circuit (including at least a transistor and a memory) formed into a chip by processing a semiconductor wafer, and is provided with an electrode that is a connection terminal.
A semiconductor circuit (IC chip) of an LSI, a CPU, a memory, or the like is mounted on a circuit board, for example, a printed wiring board, to be used as one of components of a variety of electronic devices.
A technique by which a transistor is formed using a semiconductor thin film formed over a substrate having an insulating surface has attracted attention. The transistor is used in a wide range of electronic devices such as an integrated circuit (IC) and an image display device (also simply referred to as a display device). A silicon-based semiconductor material is widely known as a material for a semiconductor thin film that can be used in a transistor. As another material, an oxide semiconductor has been attracting attention.
 It is known that a transistor including an oxide semiconductor has an extremely low leakage current in an off state. For example, Patent Document 1 discloses a low-power CPU utilizing a characteristic of a low leakage current of the transistor including an oxide semiconductor. Furthermore, for example, Patent Document 2 discloses a storage device that can retain stored data for a long time by utilizing a characteristic of a low leakage current of the transistor including an oxide semiconductor.
Patent Document 3 discloses a transistor with a minute structure in which a source electrode layer and a drain electrode layer are provided in contact with a top surface of an oxide semiconductor.
 REFERENCES Patent Documents

-   [Patent Document 1] Japanese Published Patent Application No.     2012-257187 -   [Patent Document 2] Japanese Published Patent Application No.     2011-151383 -   [Patent Document 3] PCT International Publication No. WO2016/125052

SUMMARY OF THE INVENTION

An object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a semiconductor device that operates at high speed. Another object of one embodiment of the present invention is to provide a semiconductor device with favorable electrical characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with a small variation in electrical characteristics of transistors. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device with a high on-state current. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption. Another object of one embodiment of the present invention is to provide a novel semiconductor device. Another object of one embodiment of the present invention is to provide a method of manufacturing a semiconductor device with high productivity. Another object of one embodiment of the present invention is to provide a method of manufacturing of a novel semiconductor device.
 Another object of one embodiment of the present invention is to provide a storage device having large storage capacity. Another object of one embodiment of the present invention is to provide a storage device that operates at high speed. Another object of one embodiment of the present invention is to provide a storage device with low power consumption. Another object of one embodiment of the present invention is to provide a novel storage device.
Note that the description of these objects does not preclude the existence of other objects. One embodiment of the present invention does not need to achieve all of these objects. Other objects can be derived from the description of the specification, the drawings, and the claims.
 One embodiment of the present invention is a method of manufacturing a semiconductor device, including the steps of: forming an oxide over a substrate, a first conductor over the oxide, and a second conductor over the first conductor; forming a first insulator to cover the oxide, the first conductor, and the second conductor; forming an opening in the first insulator; dividing the second conductor into a third conductor and a fourth conductor by the opening; forming a second insulator to cover the oxide and the first insulator; forming a third insulator over the second insulator; processing the second insulator and the third insulator by a dry etching method into a fourth insulator in contact with a side surface of the first insulator, a side surface of the third conductor, and a side surface of the fourth conductor and a fifth insulator in contact with a side surface and a top surface of the fourth insulator; processing the first conductor by a dry etching method using the fourth insulator and the fifth insulator as a mask to divide the first conductor into a fifth conductor and a sixth conductor; removing the fifth insulator by isotropic etching; performing heat treatment on the oxide in an atmosphere containing oxygen; forming a sixth insulator to cover the oxide, the first insulator, and the fourth insulator; forming a seventh conductor over the sixth insulator; and processing the sixth insulator and the seventh conductor by CMP treatment to form a seventh insulator and an eighth conductor in the opening. A nitride insulator is formed as the second insulator and an oxide insulator is formed as the third insulator.
In the above method, silicon nitride is preferably formed by a PEALD method as the second insulator.
 In the above method, silicon oxide is preferably formed by a PEALD method as the third insulator.
In the above method, tantalum nitride is preferably formed by a sputtering method as the first conductor.
In the above method, tungsten is preferably formed by a sputtering method as the second conductor.
In the above method, oxide containing indium, gallium, and zinc is preferably formed by a sputtering method as the oxide.
One embodiment of the present invention can provide a semiconductor device that can be miniaturized or highly integrated. One embodiment of the present invention can provide a semiconductor device that operates at high speed. One embodiment of the present invention can provide a semiconductor device with favorable electrical characteristics. One embodiment of the present invention can provide a semiconductor device with a small variation in electrical characteristics of transistors. One embodiment of the present invention can provide a highly reliable semiconductor device. One embodiment of the present invention can provide a semiconductor device with a high on-state current. One embodiment of the present invention can provide a semiconductor device with low power consumption. One embodiment of the present invention can provide a novel semiconductor device. One embodiment of the present invention can provide a method of manufacturing a semiconductor device with high productivity. One embodiment of the present invention can provide a method of manufacturing of a novel semiconductor device.
One embodiment of the present invention can provide a storage device having large storage capacity. One embodiment of the present invention can provide a storage device that operates at high speed. One embodiment of the present invention can provide a storage device with low power consumption. One embodiment of the present invention can provide a novel storage device.
 Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not need to have all of these effects. Other effects can be derived from the description of the specification, the drawings, and the claims.
BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a plan view illustrating an example of a semiconductor device.
FIGS. 1B to 1D are cross-sectional views illustrating the example of a semiconductor device.
FIGS. 2A and 2B are cross-sectional views illustrating an example of a semiconductor device.
FIGS. 3A to 3C are cross-sectional views illustrating examples of a semiconductor device.
FIGS. 4A to 4D are cross-sectional views illustrating examples of a semiconductor device.
FIG. 5A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 5B to 5D are cross-sectional views illustrating the example of a manufacturing method of a semiconductor device.
FIG. 6A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 6B to 6D are cross-sectional views illustrating the example of a manufacturing method of a semiconductor device.
FIG. 7A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 7B to 7D are cross-sectional views illustrating the example of a manufacturing method of a semiconductor device.
FIG. 8A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 8B to 8D are cross-sectional views illustrating the example of a manufacturing method of a semiconductor device.
FIG. 9A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 9B to 9D are cross-sectional views illustrating the example of a manufacturing method of a semiconductor device.
 FIG. 10A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 10B to 10D are cross-sectional views illustrating the example of a manufacturing method of a semiconductor device.
FIG. 11A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 11B to 11D are cross-sectional views illustrating the example of a manufacturing method of a semiconductor device.
FIG. 12A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 12B to 12D are cross-sectional views illustrating the example of a manufacturing method of a semiconductor device.
FIG. 13A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 13B to 13D are cross-sectional views illustrating the example of a manufacturing method of a semiconductor device.
FIGS. 14A to 14C are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device.
FIG. 15A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 15B to 15D are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device.
FIGS. 16A to 16C are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device.
FIG. 17A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 17B to 17D are cross-sectional views illustrating the example of a manufacturing method of a semiconductor device.
FIG. 18A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 18B to 18D are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device.
FIG. 19 is a block diagram illustrating an example of a storage device.
 FIGS. 20A and 20B are a schematic view and a circuit diagram, respectively, illustrating an example of a storage device.
FIGS. 21A and 21B are schematic views illustrating examples of a storage device.
FIG. 22 is a circuit diagram illustrating an example of a storage device.
FIG. 23 is a cross-sectional view illustrating an example of a storage device.
FIG. 24 is a cross-sectional view illustrating an example of a storage device.
FIGS. 25A to 25C are circuit diagrams illustrating examples of storage devices.
FIGS. 26A and 26B illustrate examples of semiconductor devices.
FIGS. 27A and 27B illustrate examples of electronic components.
FIGS. 28A and 28B illustrate examples of electronic devices and FIGS. 28C to 28E illustrate an example of a large computer.
FIG. 29 illustrates an example of a device for space.
FIG. 30 illustrates an example of a storage system that can be used for a data center.
DETAILED DESCRIPTION OF THE INVENTION

Embodiments will be described in detail with reference to the drawings. Note that the present invention is not limited to the following description, and it will be readily appreciated by those skilled in the art that modes and details of the present invention can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description in the following embodiments.
Note that in structures of the invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and the description thereof is not repeated. The same hatching pattern is used for portions having similar functions, and the portions are not especially denoted by reference numerals in some cases.
 The position, size, range, or the like of each component illustrated in drawings does not represent the actual position, size, range, or the like in some cases for easy understanding. Therefore, the disclosed invention is not necessarily limited to the position, size, range, or the like disclosed in the drawings.
Note that in this specification and the like, ordinal numbers such as “first” and “second” are used for convenience and do not limit the number of components or the order of components (e.g., the order of steps or the stacking order of layers). Furthermore, an ordinal number used for a component in a certain part in this specification is not the same as an ordinal number used for the component in another part in this specification or claims in some cases.
Note that the terms “film” and “layer” can be used interchangeably depending on the case or the circumstances. For example, the term “conductive layer” can be replaced with the term “conductive film”. As another example, the term “insulating film” can be replaced with the term “insulating layer”. The term “conductor” can be replaced with the term “conductive layer” or “conductive film” depending on the case or the circumstances. The term “insulator” can be replaced with the term “insulating layer” or “insulating film” depending on the case or the circumstances.
Examples of the opening include a groove and a slit. A region where the opening is formed may be referred to as an opening portion.
In the drawings used in embodiments in this specification, a sidewall of an insulator in an opening is perpendicular or substantially perpendicular to a substrate surface or a formation surface, but the sidewall may have a tapered shape.
 In this specification and the like, a tapered shape refers to a shape such that at least part of a side surface of a component is inclined with respect to a substrate surface or a formation surface of the component. For example, a tapered shape refers to a shape including a region where the angle between the inclined side surface and the substrate surface or the formation surface of the component (hereinafter, such an angle is referred to as a taper angle in some cases) is less than 90°. Note that the side surface of the component and the substrate plane are not necessarily completely flat and may be substantially flat with a slight curvature or with slight unevenness.
Embodiment 1

In this embodiment, a semiconductor device including an oxide semiconductor and a method of manufacturing the semiconductor device will be described with reference to FIGS. 1A to 1D to FIGS. 18A to 18D.
 <Structure Example of Semiconductor Device>

An example of a structure of a semiconductor device is described with reference to FIGS. 1A to 1D to FIGS. 4A to 4D. FIGS. 1A to 1D are a plan view and cross-sectional views of a semiconductor device (a transistor 200). FIG. 1A is the plan view of the semiconductor device. FIGS. 1B to 1D are the cross-sectional views of the semiconductor device. FIG. 1B illustrates a cross section taken along the dashed-dotted line A1-A2 in FIG. 1A, which corresponds to a cross-sectional view of the transistor 200 in the channel length direction. FIG. 1C illustrates a cross section taken along the dashed-dotted line A3-A4 in FIG. 1A, which corresponds to a cross-sectional view of the transistor 200 in the channel width direction. FIG. 1D illustrates a cross section taken along the dashed-dotted line A5-A6 in FIG. 1A, which corresponds to a cross-sectional view of the transistor 200 in the channel width direction. Note that for simplification, some components are not illustrated in the plan view of FIG. 1A. FIGS. 2A and 2B to FIGS. 4A to 4D are enlarged cross-sectional views of the transistor 200 in the channel length direction.
 The transistor 200 includes a conductor 205 (a conductor 205 a and a conductor 205 b) embedded in an insulator 216, an insulator 221 over the insulator 216 and the conductor 205, an insulator 222 over the insulator 221, an insulator 224 over the insulator 222, an oxide 230 (an oxide 230 a and an oxide 230 b) over the insulator 224, a conductor 242 a (a conductor 242 a 1 and a conductor 242 a 2) and a conductor 242 b (a conductor 242 b 1 and a conductor 242 b 2) over the oxide 230, an insulator 271 a over the conductor 242 a, an insulator 271 b over the conductor 242 b, an insulator 250 over the oxide 230, and a conductor 260 (a conductor 260 a and a conductor 260 b) over the insulator 250.
An insulator 275 is provided over the insulators 271 a and 271 b, and an insulator 280 is provided over the insulator 275. An insulator 255, the insulator 250, and the conductor 260 are provided in an opening formed in the insulator 280 and the insulator 275. An insulator 282 is provided over the insulator 280 and the conductor 260. An insulator 283 is provided over the insulator 282. An insulator 215 is provided below the insulator 216 and the conductor 205. The insulator 255 is provided between the insulator 250 and the conductor 242 a 2, the conductor 242 b 2, the insulator 271 a, the insulator 271 b, the insulator 275, and the insulator 280.
 The oxide 230 includes a region that functions as a channel formation region of the transistor 200. The conductor 260 includes a region that functions as a first gate electrode (an upper gate electrode) of the transistor 200. The insulator 250 includes a region that functions as a first gate insulator of the transistor 200. The conductor 205 includes a region that functions as a second gate electrode (a lower gate electrode) of the transistor 200. Each of the insulator 224, the insulator 222, and the insulator 221 includes a region that functions as a second gate insulator of the transistor 200.
 The conductor 242 a includes a region that functions as one of a source electrode and a drain electrode of the transistor 200. The conductor 242 b includes a region that functions as the other of the source electrode and the drain electrode of the transistor 200. The conductor 242 a has a stacked-layer structure of the conductor 242 a 1 and the conductor 242 a 2 over the conductor 242 a 1. The conductor 242 b has a stacked-layer structure of the conductor 242 b 1 and the conductor 242 b 2 over the conductor 242 b 1. The conductors 242 a 1 and 242 b 1 in contact with the oxide 230 b are preferably conductors that are not easily oxidized, such as metal nitride. In that case, the conductors 242 a and 242 b can be prevented from being oxidized excessively due to oxygen contained in the oxide 230 b. The conductors 242 a 2 and 242 b 2 are preferably conductors having higher conductivity than the conductors 242 a 1 and 242 b 1, such as a metal layer. Thus, the conductors 242 a and 242 b can function as a wiring or an electrode with high conductivity. In this manner, a semiconductor device in which the conductors 242 a and 242 b which function as a wiring or an electrode are provided in contact with a top surface of the oxide 230 functioning as an active layer can be provided.
 The insulator 255 is preferably an insulator that is not easily oxidized, such as nitride. By anisotropic etching, the insulator 255 is formed in a sidewall shape to be in contact with a sidewall of the opening formed in the insulator 280 and the like (here, the sidewall of the opening corresponds to, for example, a side surface of the insulator 280 or the like in the opening). The insulator 255 is formed in contact with side surfaces of the conductors 242 a 2 and 242 b 2 and has a function of protecting the conductors 242 a 2 and 242 b 2. Although the details will be described later, heat treatment in an atmosphere containing oxygen is preferably performed after the separation of the conductor into the conductor 242 a 1 and the conductor 242 b 1 and before the formation of the insulator 250. At this time, since the insulator 255 is formed in contact with the side surfaces of the conductor 242 a 2 and the conductor 242 b 2, excessive oxidation of the conductors 242 a 2 and 242 b 2 can be prevented.
 The opening formed in the insulator 280 and the insulator 275 overlap with a region between the conductors 242 a 2 and 242 b 2. In a top view, the side surface of the insulator 280 in the opening is aligned or substantially aligned with a side surface of the conductor 242 a 2 and a side surface of the conductor 242 b 2. A part of a top surface of the conductor 242 a 1 is in contact with the conductor 242 a 2, and a part of a top surface of the conductor 242 b 1 is in contact with the conductor 242 b 2. Accordingly, the insulator 255 is in contact with another part of the top surface of the conductor 242 a 1, another part of the top surface of the conductor 242 b 1, the side surface of the conductor 242 a 2, and the side surface of the conductor 242 b 2 in the opening. Here, as illustrated in FIGS. 1B and 1C, projecting portions are formed in portions of the insulator 255 in contact with the top surface of the conductor 242 a 1, the top surface of the conductor 242 b 1, or a top surface of the insulator 222. Each of the projecting portions of the insulator 255 extends toward the center of the opening beyond the other portion of the insulator 255. Thus, the projecting portions of the insulator 255, a part of the conductor 242 a 1, and a part of the conductor 242 b 1 are formed to extend in the opening.
 The insulator 250 is in contact with the top surface of the oxide 230, a side surface of the conductor 242 a 1, a side surface of the conductor 242 b 1, and a side surface of the insulator 255. Since the projecting portions of the insulator 255, the part of the conductor 242 a 1, and the part of the conductor 242 b 1 extend in the opening, the shape of the insulator 250 is reflected by the shapes of the projecting portions of the insulator 255, the part of the conductor 242 a 1, and the part of the conductor 242 b 1.
As described above, the conductors 242 a 1 and 242 b 1 can be formed to extend beyond the conductors 242 a 2 and 242 b 2 to the same extent as the projecting portions of the insulator 255. Thus, in the cross-sectional view of the transistor 200 in the channel length direction in FIG. 2B, a distance L2 between the conductors 242 a 1 and 242 b 1 is smaller than a distance L1 between the conductors 242 a 2 and 242 b 2. With such a structure, the distance between a source and a drain can be shortened, and the channel length can also be shortened in accordance with the distance. Therefore, the frequency characteristics of the transistor 200 can be improved. By miniaturization of the semiconductor device in this manner, the semiconductor device can have improved operation speed.
 The oxide 230 preferably includes the oxide 230 a over the insulator 224 and the oxide 230 b over the oxide 230 a. When the oxide 230 a is provided below the oxide 230 b, impurities can be inhibited from diffusing into the oxide 230 b from the components formed below the oxide 230 a.
Although an example in which the oxide 230 has a two-layer structure of the oxide 230 a and the oxide 230 b is described in this embodiment, one embodiment of the present invention is not limited to this example. For example, the oxide 230 may have a single-layer structure of the oxide 230 b or a stacked-layer structure of three or more layers.
In the oxide 230 b, a channel formation region and source and drain regions of the transistor 200 are formed. The channel formation region is sandwiched between the source and drain regions. At least a part of the channel formation region overlaps with the conductor 260. The source region overlaps with the conductor 242 a, and the drain region overlaps with the conductor 242 b. Note that the source region and the drain region can be interchanged with each other.
The channel formation region has a smaller amount of oxygen vacancies or a lower impurity concentration than the source and drain regions, and thus has a low carrier concentration and a high resistance. Thus, the channel formation region can be regarded as an i-type (intrinsic) or substantially i-type region.
 The source and drain regions have a large amount of oxygen vacancies or a high concentration of impurities such as hydrogen, nitrogen, or a metal element, and thus are low-resistance regions with a high carrier concentration. In other words, the source and drain regions are n-type regions (low-resistance regions) having a higher carrier concentration than the channel formation region.
Note that the carrier concentration in the channel formation region is preferably lower than or equal to 1×10¹⁸ cm⁻³, lower than 1×10¹⁷ cm⁻³, lower than 1×10¹⁶ cm⁻³, lower than 1×10¹⁵ cm⁻³, lower than 1×10¹⁴ cm⁻³, lower than 1×10¹³ cm⁻³, lower than 1×10¹² cm⁻³, lower than 1×10¹¹ cm⁻³, or lower than 1×10¹⁰ cm⁻³. The lower limit of the carrier concentration of the channel formation region is not particularly limited and can be, for example, 1×10⁻⁹ cm⁻³.
In order to reduce the carrier concentration of the oxide 230 b, the impurity concentration in the oxide 230 b is reduced so that the density of defect states is reduced. In this specification and the like, a state with a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic state. Note that an oxide semiconductor (or metal oxide) having a low carrier concentration may be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.
 To obtain stable electrical characteristics of the transistor 200, it is effective to reduce the concentration of impurities in the oxide 230 b. In order to reduce the concentration of impurities in the oxide 230 b, the concentration of impurities also in a film adjacent to the oxide 230 b is preferably reduced. Examples of impurities include hydrogen, nitrogen, an alkali metal, an alkaline earth metal, iron, nickel, and silicon. Note that an impurity in the oxide 230 b refers to, for example, elements other than the main components of the oxide 230 b. For example, an element with a concentration lower than 0.1 atomic % is regarded as an impurity.
Note that the channel formation region, the source region, and the drain region may be formed not only in the oxide 230 b but also in the oxide 230 a.
In the oxide 230, the boundaries between the regions are difficult to clearly observe in some cases. The concentration of a metal element and an impurity element such as hydrogen or nitrogen, which is detected in each region, may be gradually changed not only between the regions but also in each region. That is, the region closer to the channel formation region may have a lower concentration of a metal element and an impurity element such as hydrogen or nitrogen.
A metal oxide functioning as a semiconductor (hereinafter such a metal oxide is also referred to as an oxide semiconductor) is preferably used for the oxide 230 (the oxides 230 a and 230 b).
 The band gap of the metal oxide functioning as a semiconductor is preferably greater than or equal to 2.0 eV, further preferably greater than or equal to 2.5 eV. The use of such metal oxide having a wide band gap can reduce the off-state current of the transistor. A transistor including metal oxide in a channel formation region is referred to as an OS transistor. The off-state current of the OS transistor is small, so that power consumption of the semiconductor device can be sufficiently reduced. The OS transistor has high frequency characteristics, which enables the semiconductor device to operate at high speed.
 The oxide 230 preferably includes metal oxide (an oxide semiconductor). Examples of the metal oxide that can be used for the oxide 230 include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably contains at least indium (In) or zinc (Zn). The metal oxide preferably contains two or three selected from indium, an element M, and zinc. The element M is a metal element or metalloid element having a high bonding energy with oxygen. For example, the bonding energy of the metal element or metalloid element with oxygen is higher than that of indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M included in the metal oxide is preferably one or more of the above elements, further preferably one or more selected from aluminum, gallium, tin, and yttrium, still further preferably gallium. Note that in this specification and the like, a metal element and a metalloid element are collectively referred to as a “metal element” in some cases, and a “metal element” described in this specification and the like includes a metalloid element in some cases.
 As the oxide 230, indium zinc oxide (In—Zn oxide), indium tin oxide (In—Sn oxide), indium titanium oxide (In—Ti oxide), indium gallium oxide (In—Ga oxide), indium gallium aluminum oxide (In—Ga—Al oxide), indium gallium tin oxide (In—Ga—Sn oxide), gallium zinc oxide (also referred to as Ga—Zn oxide or GZO), aluminum zinc oxide (also referred to as Al—Zn oxide or AZO), indium aluminum zinc oxide (also referred to as In—Al—Zn oxide or IAZO), indium tin zinc oxide (In—Sn—Zn oxide), indium titanium zinc oxide (In—Ti—Zn oxide), indium gallium zinc oxide (also referred to as In-Ga—Zn oxide or IGZO), indium gallium tin zinc oxide (also referred to as In—Ga—Sn—Zn oxide or IGZTO), or indium gallium aluminum zinc oxide (also referred to as In—Ga—Al—Zn oxide, IGAZO, or IAGZO) can be used, for example. Alternatively, indium tin oxide containing silicon, gallium tin oxide (Ga—Sn oxide), aluminum tin oxide (Al—Sn oxide), or the like can be used.
By increasing the proportion of indium atoms in the sum of atoms of all metal elements included in the metal oxide, the field-effect mobility of the transistor can be increased.
 Instead of indium or in addition to indium, the metal oxide may contain one or more kinds of metal elements whose period number in the periodic table is large. As an overlap of orbitals of metal elements becomes larger, the carrier conduction in the metal oxide is likely to be large. Thus, when a metal element with a large period number is included in the metal oxide, the field-effect mobility of the transistor can be increased in some cases. As examples of the metal element with a large period number, metal elements belonging to Period 5 or 6 in the periodic table are given. Specific examples of the metal element include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare-earth elements.
The metal oxide may contain one or more kinds of non-metal elements. The metal oxide containing a non-metal element can increase the field-effect mobility of a transistor in some cases. Examples of the non-metal element include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.
By increasing the proportion of zinc atoms in the sum of atoms of all metal elements included in the metal oxide, the metal oxide has high crystallinity, so that diffusion of impurities in the metal oxide can be inhibited. Consequently, changes in the electrical characteristics of the transistor can be reduced to improve the reliability of the transistor.
 By increasing the proportion of the element M atoms in the sum of atoms of all metal elements included in the metal oxide, oxygen vacancies can be prevented from being formed in the metal oxide. Accordingly, generation of carriers due to oxygen vacancies is inhibited, which makes the off-state current of the transistor small. Furthermore, changes in the electrical characteristics of the transistor can be reduced to improve the reliability of the transistor.
As described above, electrical characteristics and reliability of a transistor are changed depending on the composition of metal oxide used for the oxide 230. Therefore, by changing the composition of the metal oxide in accordance with electrical characteristics and reliability required for the transistor, a semiconductor device having both excellent electrical characteristics and high reliability can be achieved.
The oxide 230 preferably has a stacked-layer structure of oxide layers with different chemical compositions. For example, the atomic ratio of the element M to a metal element that is the main component in the metal oxide used as the oxide 230 a is preferably higher than that in the metal oxide used as the oxide 230 b. The atomic ratio of the element M to In in the metal oxide used as the oxide 230 a is preferably higher than that in the metal oxide used as the oxide 230 b. This structure can inhibit impurities and oxygen from diffusing into the oxide 230 b from the components formed below the oxide 230 a.
The atomic ratio of In to the element M in the metal oxide used as the oxide 230 b is preferably higher than that in the metal oxide used as the oxide 230 a. With this structure, the transistor 200 can have high on-state current and high frequency characteristics.
 When the oxide 230 a and the oxide 230 b contain a common element as the main component besides oxygen, the density of defect states at the interface between the oxide 230 a and the oxide 230 b can be low. This reduces the influence of interface scattering on carrier conduction, and the transistor 200 can have a high on-state current and high frequency characteristics.
Specifically, as the oxide 230 a, a metal oxide having an atomic ratio of In:M:Zn=1:3:2 or a neighborhood thereof, In:M:Zn=1:3:4 or a neighborhood thereof, or In:M:Zn=1:1:0.5 or a neighborhood thereof can be used. As the oxide 230 b, a metal oxide having an atomic ratio of In:M:Zn=1:1:1 or a neighborhood thereof, In:M:Zn=1:1:1.2 or a neighborhood thereof, In:M:Zn=1:1:2 or a neighborhood thereof, or In:M:Zn=4:2:3 or a neighborhood thereof can be used. Note that the neighborhood of an atomic ratio includes ±30% of an intended atomic ratio. Gallium is preferably used as the element M. In the case where a single layer of the oxide 230 b is provided as the oxide 230, metal oxide that can be used as the oxide 230 a may be used as the oxide 230 b. The compositions of the metal oxide that can be used as the oxide 230 a and the oxide 230 b are not limited to the above. For example, the composition of metal oxide that can be used as the oxide 230 a can be applied to the oxide 230 b. Similarly, the composition of metal oxide that can be used as the 230 b can be applied to the oxide 230 a.
 When the metal oxide is deposited by a sputtering method, the above atomic ratio is not limited to the atomic ratio of the deposited metal oxide and may be the atomic ratio of a sputtering target used for depositing the metal oxide.
The oxide 230 b preferably exhibits crystallinity. In particular, as the oxide 230 b, a c-axis-aligned crystalline oxide semiconductor (CAAC-OS) is preferably used.
The CAAC-OS is a metal oxide having a dense structure with high crystallinity and a low amount of impurities and defects (e.g., oxygen vacancies). In particular, after the formation of a metal oxide, heat treatment is performed at a temperature at which the metal oxide does not become a polycrystal (e.g., higher than or equal to 400° C. and lower than or equal to 600° C.), whereby a CAAC-OS having a dense structure with higher crystallinity can be obtained. As the density of the CAAC-OS is increased in such a manner, diffusion of impurities or oxygen in the CAAC-OS can be further reduced.
In the CAAC-OS, a reduction in electron mobility due to a crystal grain boundary is less likely to occur because it is difficult to observe a clear crystal grain boundary. Thus, a metal oxide including the CAAC-OS is physically stable. Accordingly, the metal oxide including the CAAC-OS is resistant to heat and has high reliability.
When an oxide having crystallinity, such as CAAC-OS, is used as the oxide 230 b, oxygen extraction from the oxide 230 b by source or drain electrodes can be inhibited. In this case, extraction of oxygen from the oxide 230 b can be inhibited even when heat treatment is performed; hence, the transistor 200 is stable against high temperatures in the manufacturing process (i.e., thermal budget).
 If impurities and oxygen vacancies exist in a channel formation region of an oxide semiconductor, a transistor including the oxide semiconductor might have variable electrical characteristics and poor reliability. In some cases, a defect that is an oxygen vacancy into which hydrogen enters (hereinafter also referred to as VoH in some cases) generates an electron serving as a carrier. Therefore, when the channel formation region in the oxide semiconductor includes oxygen vacancies, the transistor tends to have normally-on characteristics (the channel is generated even when no voltage is applied to the gate electrode and current flows through the transistor). Thus, impurities, oxygen vacancies, and VoH are preferably reduced as much as possible in the channel formation region in the oxide semiconductor. In other words, the channel formation region in the oxide semiconductor is an i-type (intrinsic) or substantially i-type region with a low carrier concentration.
