FIG. 8 is a timing chart illustrating operation of the solid state imaging device according to this modified example. When the FD voltage VFD is higher than or equal to the brightness determination voltage Vjdg, the signal output from the comparator 501 is low level and the switch 702 is in a non-conductive state causing the same operation as that in FIG. 3 of the first embodiment to be performed. When the FD voltage VFD is lower than the brightness determination voltage Vjdg, the signal output from the comparator 501 is high level and the switch 702 is in a conductive state, which results in a reduced slope of the ramp wave voltage VRAMP. Since a reduced slope of the ramp wave voltage VRAMP results in the reduced number of pulses, power consumption is reduced. In such a way, in this modified example, by reducing the slope of the ramp wave voltage VRAMP only in the case of high brightness, power consumption can be reduced in the case of high brightness while maintaining the advantage of improving the gradation property for a low-brightness object.
 Here, weighting operation in this modified example will be described. In the present embodiment, the slope of the ramp wave voltage VRAMP decreases at the time of high brightness. Since this slope depends on the capacitance of the integration capacitor 207 and the capacitance of the integration capacitor 703, the AD conversion value is weighted with coefficients corresponding thereto. For example, when the ratio of the capacitances of the integration capacitor 207 and the integration capacitor 703 is 1:1, doubling the AD conversion value of the S signal at the time of high brightness for weighting operation allows for obtaining the AD conversion value corresponding to the actual brightness. Specifically, in the case of the example illustrated in FIG. 8, since the AD conversion value of the N signal is four while the AD conversion value of the S signal is eight at the time of low brightness, the AD conversion value of the optical signal obtained by the S-N process is four that equals to 8-4. On the other hand, the AD conversion value of the N signal is four while the AD conversion value of the S signal is also five at the time of high brightness. Since the weighting operation of doubling the AD conversion value of the S signal is then performed, the AD conversion value of the optical signal obtained by the S-N process is six that equals to 5×2-4. In further generalization, when the ratio of the capacitances of the integration capacitor 207 and the integration capacitor 703 is 1:q, weighting operation of multiplying the AD conversion value at the time of high brightness by (q+1) allows for obtaining an AD conversion value corresponding to the actual brightness.
 Fourth Embodiment

A fourth embodiment of the present invention will be described. A solid state imaging device according to the present embodiment is the same as the solid state imaging device according to the first embodiment described above except the configuration and operation timing of the preceding stage of the ramp wave generating unit 205. Thus, portions which are different from the first embodiment will be described below, and description of the portions having the same configuration as in the first embodiment will be omitted or simplified.
 FIG. 9 is a circuit diagram illustrating a configuration of a pixel 900 according to the present embodiment. The pixel 900 of the present embodiment has two PDs within a single pixel and has a pixel configuration that enables global shutter operation in which the accumulation start time and the accumulation end time are matched in all the pixels. Thus, the pixel 900 has PDs 201 a and 201 b, holding capacitors 902 a and 902 b, and transfer switches 901 a, 901 b, 202 a, and 202 b. The transfer switches 901 a and 901 b are controlled to be in a conductive state or a non-conductive state by a control signal PGS(m) output from the vertical scanning circuit 101. The transfer switch 202 a is controlled to be in a conductive state or a non-conductive state by a control signal PTXa(m) output from the vertical scanning circuit 101. The transfer switch 202 b is controlled to be in a conductive state or a non-conductive state by a control signal PTXb(m) output from the vertical scanning circuit 101. Note that the capability of performing global shutter operation is not essential and, in such a case, the transfer switches 901 a and 901 b and the holding capacitors 902 a and 902 b may be omitted, for example.
 The anode of the PD 201 a (the first photoelectric conversion unit) is grounded and the cathode thereof is connected to one terminal of the transfer switch 901 a (the first transfer unit). The other terminal of the transfer switch 901 a is connected to one terminal of the holding capacitor 902 a (the third capacitor element) and one terminal of the transfer switch 202 a (the second transfer unit). The other terminal of the holding capacitor 902 a is grounded. In response to the transfer switch 901 a entering a conductive state by the control signal PGS(m), charges accumulated in the PD 201 a are transferred to the holding capacitor 902 a. The other terminal of the transfer switch 202 a is connected to the FD 203. In response to the transfer switch 202 a entering a conductive state by the control signal PTXa(m), charges accumulated in the holding capacitor 902 a are transferred to the FD 203.
 The anode of the PD 201 b (the second photoelectric conversion unit) is grounded and the cathode thereof is connected to one terminal of the transfer switch 901 b (the third transfer unit). The other terminal of the transfer switch 901 b is connected to one terminal of the holding capacitor 902 b (the fourth capacitor element) and one terminal of the transfer switch 202 b (the fourth transfer unit). The other terminal of the holding capacitor 902 b is grounded. In response to the transfer switch 901 b entering a conductive state by the control signal PGS(m), charges accumulated in the PD 201 b are transferred to the holding capacitor 902 b. The other terminal of the transfer switch 202 b is connected to the FD 203. In response to the transfer switch 202 b entering a conductive state by the control signal PTXb(m), charges accumulated in the holding capacitor 902 b are transferred to the FD 203.
 FIG. 10A is a timing chart illustrating operation of the solid state imaging device of the present embodiment. FIG. 10A depicts the control signals PRES1, PRES2, PGS, PTXa, PTXb, the FD voltage VFD, the ramp wave voltage VRAMP, and the count value COUNT. Furthermore, FIG. 10A depicts digital values stored in the N data storage area NMEM, an Sa data storage area SaMEM, and an Sb data storage area SbMEM, respectively. Note that the timing chart of FIG. 10A illustrates the operation timing on a certain row of the pixel array 900, and the row number of each control signal is omitted. While operation on a particular row only of the pixel array 900 will be focused on and described below, the operation of FIG. 10A is performed simultaneously on all the rows. Since exposure time is not different among rows, a capturing without a rolling shutter distortion is possible.
In a period from the time T21 to the time T22, all the control signals PRES1, PRES2, PGS, PTXa, and PTXb are high level. Thereby, the FD reset switch 204, the ramp wave reset switch 208, and the transfer switches 901 a, 901 b, 202 a, and 202 b enter a conductive state. This operation causes the PDs 201 a and 201 b, the holding capacitors 902 a and 902 b, and the FD 203 to be reset to the pixel reset voltage SVDD, and the output of the ramp wave generating unit 205 is reset to the ground potential.
 At the time T22, the control signals PGS, PTXa, and PTXb become low level, and the transfer switches 901 a, 901 b, 202 a, and 202 b enter a non-conductive state. From the time T22, the PDs 201 a and 201 b start accumulation of charges generated due to an incident light.
Then, the control signal PGS becomes high level at the time T23, and the control signal PGS again becomes low level at the time T24. That is, the transfer switches 901 a and 901 b are in a conductive state in a period from the time T23 to the time T24, which causes charges accumulated in the PDs 201 a and 201 b to be transferred to the holding capacitors 902 a and 902 b, respectively. A period from the time T22 at which the PDs 201 a and 201 b start accumulation of charges to the time T24 at the end of transfer of charges to the holding capacitors 902 a and 902 b is denoted as accumulation period.
At the time T25, the control signal PRES1 then becomes low level, and the FD reset switch 204 enters a non-conductive state. At this time, the FD voltage VFD becomes a level of the N signal. Subsequently, at the time T26, the control signal PRES2 becomes low level, and the ramp wave reset switch 208 enters a non-conductive state. Thereby, the ramp wave voltage VRAMP starts increasing, and AD conversion of the N signal is started. In the N-AD period from the time T26 to the time T27 at which the control signal PRES2 becomes high level and the ramp wave reset switch 208 enters a non-conductive state, AD conversion of the N signal is performed in the same manner as in the first embodiment.
 At the time T28, the control signal PTXa then becomes high level, and the transfer switch 202 a enters a conductive state. This operation causes charges held in the holding capacitor 902 a to be transferred to the FD 203, and the FD voltage VFD decreases. The FD voltage VFD at this time is denoted as Sa signal. At the time T29, the control signal PTXa becomes low level, and the transfer switch 202 a enters a non-conductive state. Thereby, transfer of charges ends.
In a period from the time T30 to the time T31, the control signal PRES2 is low level, and AD conversion of the Sa signal is performed by the same process as that in the N-AD period. In a period from the time T30 at which the control signal PRES2 becomes low level to the time T31 at which it again becomes high level, that is, the AD conversion period of the Sa signal is denoted as Sa-AD period.
At the time T32, the control signal PTXb then becomes high level, and the transfer switch 202 b enters a conductive state. This operation causes charges held in the holding capacitor 902 b to be transferred to the FD 203, and the FD voltage VFD decreases. The FD voltage VFD at this time is denoted as Sb signal. At the time T33, the control signal PTXb becomes low level, and the transfer switch 202 b enters a non-conductive state. Thereby, transfer of charges ends.
 In a period from the time T34 to the time T35, the control signal PRES2 is low level, and AD conversion of the Sb signal is performed by the same process as that in the N-AD period and the Sa-AD period. A period from the time T34 at which the control signal PRES2 becomes low level to the time T35 at which it again becomes high level, that is, the AD conversion period of the Sb signal is denoted as Sb-AD period.
The AD conversion value of the Sa signal contains the N signal and a first optical signal that is the signal component of charges generated in the PD 201 a by photoelectric conversion. The AD conversion value of the Sb signal contains the Sa signal and a second optical signal that is the signal component of charges generated in the PD 201 b by photoelectric conversion. Thus, the AD conversion value of the first optical signal is obtained by acquiring the difference between the AD conversion value of the Sa signal and the AD conversion value of the N signal. Further, the AD conversion value of the second optical signal is obtained by acquiring the difference between the AD conversion value of the Sb signal and the AD conversion value of the Sa signal. Calculation of these differences is performed in the memory 211 or the DFE 102, for example.
According to the present embodiment, the same advantages as those in the first embodiment can be obtained even with the pixel configuration having two PDs within a single pixel. Further, global shutter operation is made possible in the pixel configuration having two PDs within a single pixel.
 A modified example of the present embodiment will be described with reference to FIG. 10B. In the present embodiment, as illustrated in FIG. 10B, an Nb-AD period may be further added between the Sa-AD period and the Sb-AD period. In the timing chart illustrated in FIG. 10B, at the time T36 at which the Sa-AD period ends, and not only the control signal PRES2 but also the control signal PRES1 becomes high level. That is, the FD reset switch 204 and the ramp wave reset switch 208 enter a conductive state, and not only the ramp wave voltage VRAMP but also the FD voltage FD voltage VFD is reset. Next, at the time T37, the control signal PRES1 becomes low level and the FD reset switch 204 enters a non-conductive state, resulting in a floating state of the FD 203. The FD voltage VFD at this time is denoted as Nb signal. Further, the FD voltage VFD immediately after the reset of the FD 203 after the end of an accumulation period, which corresponds to the N signal of FIG. 10A, is called Na signal in this modified example for the purpose of distinction from the Nb signal. Further, a period corresponding to the N-AD period of FIG. 10A is called Na-AD period in this modified example.
 At the time T38, the control signal PRES2 then becomes low level, and the ramp wave reset switch 208 enters a non-conductive state. The ramp wave voltage VRAMP output from the ramp wave generating unit 205 starts increasing, and AD conversion of the Nb signal is started. At the time T39, the control signal PRES2 becomes high level, and the ramp wave reset switch 208 enters a conductive state. Thereby, AD conversion of the Nb signal ends. A period from the time T38 to the time T39, that is, AD conversion period of the Nb signal is denoted as Nb-AD period. After the Nb-AD period, AD conversion of the Sb signal is performed in the same manner as the operation of FIG. 10A.
The AD conversion value of the Sa signal contains the Na signal and the first optical signal that is the signal component of charges generated in the PD 201 a by photoelectric conversion. The Sb signal contains the Nb signal and the second optical signal that is the signal component of charges generated in the PD 201 b by photoelectric conversion. Thus, the AD conversion value of the first optical signal is obtained by acquiring the difference between the AD conversion value of the Sa signal and the AD conversion value of the Na signal. Further, the AD conversion value of the second optical signal can be obtained by acquiring the difference between the AD conversion value of the Sb signal and the AD conversion value of the Nb signal. Calculation of these differences is performed in the memory 211 or the DFE 102, for example.
 As discussed above, the Nb-AD period can be added between the Sa-AD period and the Sb-AD period. The operation of FIG. 10A has an advantage that the time from the end of an accumulation period to the end of AD conversion can be shortened compared to the operation of FIG. 10B. In contrast, in the operation of FIG. 10B, it is not necessary to hold both charges generated by the PD 201 a and charges generated by the PD 201 b in the FD 203 at the same time. Therefore, in the operation of FIG. 10B, the maximum value of the charge amount to be held in the FD 203 is reduced compared to the operation of FIG. 10A, allowing for an advantage of improved flexibility of design.
Note that, in the present embodiment, although the case where the number of PDs within a pixel is two has been exemplified, the number of PDs within a pixel may be three or more.
Fifth Embodiment

A fifth embodiment of the present invention will be described. A solid state imaging device according to the present embodiment is formed on a plurality of stacked substrates. The circuit configuration of the solid state imaging device will be described below based on that of the first embodiment unless otherwise specified. Without being limited thereto, however, the configuration of the present embodiment is applicable to any of the first to fourth embodiments.
 FIG. 11 is a schematic diagram of the stacked structure of the solid state imaging device according to the present embodiment. FIG. 11 illustrates a sectional view in the perpendicular direction to the substrate surface on which the solid state imaging device is arranged. The solid state imaging device according to the present embodiment has a first substrate 1101 including at least the PD 201, a second substrate 1102 including at least the counter 210 and the memory 211, and a substrate connection unit 1103.
The first substrate 1101 and the second substrate 1102 each may be a semiconductor substrate whose material is silicon, for example. The substrate connection unit 1103 mechanically and electrically connects the first substrate 1101 to the second substrate 1102.
Connection portions of the substrate connection unit 1103 may be provided correspondingly to the plurality of pixels 200, respectively. For example, when a plurality of PDs are included within a pixel as seen in the fourth embodiment, connection portions may be provided correspondingly to the plurality of PDs, respectively.
The substrate connection unit 1103 may be, for example, Through Silicon Via (TSV), micro bumps, direct bonding in which electrodes formed on each of the first substrate 1101 and the second substrate 1102 are directly attached to each other, or the like. Without being limited to the above, however, any connection structure may be applied as the substrate connection unit 1103. However, since TSV requires structure for penetrating the first substrate 1101, a sufficiently large region to form the PD 201 may not be obtained. It is therefore more preferable to apply micro bumps or direct bonding that does not require penetration of the first substrate 1101.
 FIG. 12 to FIG. 14 are circuit diagrams each illustrating a circuit configuration of the pixel 200 and the relationship between the first substrate 1101 and the second substrate 1102 in the present embodiment. In FIG. 12, the PD 201 is arranged in the first substrate 1101, and other components such as the transfer switch 202 are arranged in the second substrate 1102. Further, the substrate connection unit 1103 is arranged between the PD 201 and the transfer switch 202. According to the exemplary configuration of FIG. 12, since the major part of the area of the first substrate 1101 can be used for formation of the PD 201, the area for the PD 201 can be increased, which can improve the sensitivity of the PD 201.
FIG. 13 is an exemplary configuration that is different from the configuration of FIG. 12 in that the transfer switch 202 is arranged on the first substrate 1101 instead of on the second substrate 1102. That is, the PD 201 and the transfer switch 202 are arranged on the first substrate 1101, and the remaining components are arranged on the second substrate 1102. Further, the substrate connection unit 1103 is arranged between the transfer switch 202 and the FD 203. In the exemplary configuration of FIG. 13, a parasitic capacitance occurring at the FD 203 may be larger than that in the example of FIG. 12. However, it is not necessary to form any contact to the substrate connection unit 1103 over the PD 201, which allows for an advantage of a reduced dark current noise occurring at the PD 201, and therefore the exemplary configuration of FIG. 13 may be more preferable in some cases.
 FIG. 14 illustrates an exemplary configuration that is different from the configuration of FIG. 13 in that the FD reset switch 204 and the ramp wave generating unit 205 are arranged on the first substrate 1101 instead of on the second substrate 1102. That is, the PD 201, the transfer switch 202, the FD 203, the FD reset switch 204, and the ramp wave generating unit 205 are arranged on the first substrate 1101, and the remaining components are arranged on the second substrate 1102. Further, the substrate connection unit 1103 is arranged between the output node of the ramp wave generating unit 205, and the ramp wave switch 208 and the detection unit 209.
 In the exemplary configuration of FIG. 14, all the high-withstand-voltage components (for example, 5V system, 3.3V system, or the like) can be formed on the first substrate 1101, and all the low-withstand-voltage components (for example, 1.2V system or the like) can be formed on the second substrate 1102. Furthermore, while the integration capacitor 207 may be formed on the first substrate 1101 as seen in FIG. 14, it may be formed on the second substrate 1102. In this case, by designing the film thickness between electrodes such that a formation process of an insulating film for the electrodes of the integration capacitor 207 can be shared with a formation process of an interlayer insulating film, a need for an additional process for forming the integration capacitor 207 is eliminated and the number of process steps can be reduced. More specifically, the insulating film thickness between the electrodes is designed to be thinner in the case where the integration capacitor 207 is formed on the second substrate 1102 than in the case where the integration capacitor 207 is formed on the first substrate 1101. This is because the interlayer insulating film formed on the second substrate 1102 is thinner than the interlayer insulating film formed on the first substrate 1101 due to the difference in the withstand voltage or the like. Such design of the integration capacitor 207 allows the thickness between the electrodes of the integration capacitor 207 to be adapted to the formation process of the interlayer insulating film, which can reduce the number of process steps.
 Although the control signals PTX, PRES1, and PRES2 are generated in the vertical scanning circuit 101 in the first embodiment, these functions may lie in any one of the first substrate 1101 or the second substrate 1102 in the present embodiment. For example, the control signals PTX, PRES1, and PRES2 may be generated and supplied in components formed on the substrate on which each switch that is input with each signal is arranged. Alternatively, the control signals PTX, PRES1, and PRES2 may be generated at components formed on one of the first substrate 1101 and the second substrate 1102 and supplied to the other substrate if necessary. For example, the control signals PTX, PRES1, and PRES2 may be generated on the second substrate 1102 and supplied to the first substrate 1101 via control lines included in the substrate connection unit 1103. In this case, the control lines that transmit the control signals PTX, PRES1, and PRES2 may be those connected to each pixel 200 via the inside of the pixel array 100, or those connected to each pixel 200 via the outside of the pixel array 100.
 Further, although FIG. 11 illustrates the exemplary configuration in which two substrates are stacked, the number of substrates to be stacked may be three or more. FIG. 15 is a schematic diagram illustrating the stacked structure of the solid state imaging device in which the first substrate 1101, the second substrate 1102, and a third substrate 1500 are stacked, as a modified example of the present embodiment. The substrate connection unit 1103 mechanically and electrically connects the first substrate 1101 to the second substrate 1102, and a substrate connection unit 1501 mechanically and electrically connects the second substrate 1102 to the third substrate 1500. For example, the configuration may be such that a circuit from the PD 201 to the ramp wave generating unit 205 is arranged on the first substrate 1101, a circuit from the ramp wave reset switch 208 to the memory 211 is arranged on the second substrate 1102, and a post stage circuit of the DFE 102 is arranged on the third substrate 1500. In this case, the digital value held in the memory 211 arranged on the second substrate 1102 is transmitted via the substrate connection unit 1501 to the DFE 102 arranged on the third substrate 1500. The DFE 102 functions as a digital signal processing circuit that performs predetermined signal processing such as correction, sorting, or the like on the digital value.
Sixth Embodiment

An imaging system 1600 according to a sixth embodiment of the present invention will be described by using FIG. 16. FIG. 16 is a block diagram illustrating an exemplary configuration of the imaging system 1600 of the present embodiment.
 The imaging system 1600 according to the present embodiment can be applied to, though not limited in particular, a digital still camera, a digital camcorder, a camera head, a copier machine, a fax machine, a mobile phone, an on-vehicle camera, a satellite, or the like, for example.
The imaging system 1600 has a barrier 1601, a lens 1602, a diaphragm 1603, a solid state imaging device 1604, an image processing unit 1607, a timing generating unit 1608, an entire control and calculation unit 1609, and a memory unit 1610. Further, the imaging system 1600 has a storage medium control I/F unit 1611 and an external I/F unit 1613 as an interface (I/F) to the outside of the imaging system 1600. The solid state imaging device according to any of the first to fifth embodiments can be applied to the solid state imaging device 1604.
The lens 1602 captures an optical image of an object on the solid state imaging device 1604. The diaphragm 1603 changes the light amount passing through the lens 1602. The barrier 1601 is provided for protection of the lens 1602. The solid state imaging device 1604 is the solid state imaging device described in the above embodiments and converts an optical image captured by the lens 1602 into image data.
 The image processing unit 1607 is an image processing device that performs various processes such as correction and data compression on the image signal output from the solid state imaging device 1604. The image processing unit 1607 may be mounted on at least one of one or more substrates forming the solid state imaging device 1604, or may be mounted on a separate substrate. The timing generating unit 1608 outputs various timing signals to the solid state imaging device 1604 and the image processing unit 1607. The entire control and calculation unit 1609 is an entire control unit that controls the entire imaging system 1600. Here, the timing signals or the like may be input from the outside of the imaging system 1600, and the imaging system 1600 may be any system as long as it has at least the solid state imaging device 1604 and the image processing unit 1607 that processes an image signal output from the solid state imaging device 1604.
The memory unit 1610 is a frame memory unit for temporarily storing image data. The storage medium control I/F unit 1611 is an interface unit that performs storage to a storage medium 1612 or readout from the storage medium 1612. The storage medium 1612 is a removable storage medium such as a semiconductor memory or a storage medium built in the imaging system that performs storage or readout of imaging data. The external I/F unit 1613 is an interface unit for communicating with an external computer or the like.
As discussed above, the imaging system to which the solid state imaging device according to the first to fifth embodiments is applied is configured, which can realize the imaging system that can capture an image with a good gradation property for a low-brightness object.
 Other Embodiments

The present invention can be modified in various ways without being limited to the embodiments described above. The configuration of the pixel 200 illustrated in FIG. 2 is a mere example, and the configuration of the pixel 200 that is applicable to the solid state imaging device of the present invention is not limited thereto. Further, the imaging system 1600 illustrated in the sixth embodiment is a mere example of imaging systems to which the solid state imaging device of the present invention may be applied, and the imaging system to which the solid state imaging device of the present invention can be applied is not limited to the configuration illustrated in FIG. 16.
 Embodiments of the present invention can also be realized by a computer of a system or apparatus that reads out and executes computer executable instructions (e.g., one or more programs) recorded on a storage medium (which may also be referred to more fully as a ‘non-transitory computer-readable storage medium’) to perform the functions of one or more of the above-described embodiments and/or that includes one or more circuits (e.g., application specific integrated circuit (ASIC)) for performing the functions of one or more of the above-described embodiments, and by a method performed by the computer of the system or apparatus by, for example, reading out and executing the computer executable instructions from the storage medium to perform the functions of one or more of the above-described embodiments and/or controlling the one or more circuits to perform the functions of one or more of the above-described embodiments. The computer may comprise one or more processors (e.g., central processing unit (CPU), micro processing unit (MPU)) and may include a network of separate computers or separate processors to read out and execute the computer executable instructions. The computer executable instructions may be provided to the computer, for example, from a network or the storage medium. The storage medium may include, for example, one or more of a hard disk, a random-access memory (RAM), a read only memory (ROM), a storage of distributed computing systems, an optical disk (such as a compact disc (CD), digital versatile disc (DVD), or Blu-ray Disc (BD)™), a flash memory device, a memory card, and the like.
 While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions.
This application claims the benefit of Japanese Patent Application No. 2016-105158, filed May 26, 2016, which is hereby incorporated by reference herein in its entirety.
 What is claimed is:
 1. A solid state imaging device comprising: a first photoelectric conversion unit configured to generate a signal in accordance with an incident light by photoelectric conversion; a first transfer unit configured to transfer the signal from the first photoelectric conversion unit; a ramp wave generating unit that has an input node to which the signal is transferred and configured to generate a ramp wave whose voltage changes with time at a slope in accordance with a potential of the input node; a detection unit configured to detect a change in a relationship between a voltage of the ramp wave and a threshold voltage; a ramp wave reset unit configured to reset the voltage of the ramp wave when the detection unit detects a change in the relationship between the voltage of the ramp wave and the threshold voltage; a control unit configured to cause the detection unit to repeatedly detect a change in the relationship between the voltage of the ramp wave and the threshold voltage by repeating generation of the ramp wave by the ramp wave generating unit and the reset by the ramp wave reset unit within a predetermined period; and a digital value acquisition unit configured to acquire a digital value corresponding to the number of repetitions for which a change in the relationship between the voltage of the ramp wave and the threshold voltage is detected by the detection unit within the predetermined period.
 2. The solid state imaging device according to claim 1, wherein the ramp wave generating unit comprises a first transistor configured to supply a current in accordance with the potential of the input node, and a first capacitor element configured to accumulate a signal by the current supplied from the first transistor and converts the accumulated signal into a voltage.
3. The solid state imaging device according to claim 2, wherein the ramp wave generating unit further comprises a second transistor cascode-connected between the first transistor and an output node of the ramp wave generating unit.
4. The solid state imaging device according to claim 2, wherein the ramp wave generating unit further comprises a buffer to which the potential of the input node is input, and an output potential from the buffer is input to a gate of the first transistor.
5. The solid state imaging device according to claim 2, wherein the ramp wave generating unit further comprises a second capacitor element configured to accumulate a signal by the current supplied from the first transistor and configured to convert the accumulated signal into a voltage, and a capacitor switch unit configured to cause the first transistor and the second capacitor element to enter a conductive state or a non-conductive state based on the potential of the input node.
6. The solid state imaging device according to claim 1, wherein the digital acquisition unit comprises a counter configured to acquire a count value based on the number of repetitions for which a change in the relationship between the voltage of the ramp wave and the threshold voltage is detected by the detection unit within the predetermined period, and a memory configured to store a count value acquired by the counter as the digital value.
 7. The solid state imaging device according to claim 6 further comprising a count period switch unit configured to, based on the potential of the input node, change the predetermined period in which the counter acquires the count value.
8. The solid state imaging device according to claim 1 further comprising: a third capacitor element to which the signal is transferred by the first transfer unit; and a second transfer unit configured to transfer the signal from the third capacitor element to the input node.
9. The solid state imaging device according to claim 8 further comprising: a second photoelectric conversion unit configured to generate a signal in accordance with an incident light by photoelectric conversion; a third transfer unit configured to transfer the signal from the second photoelectric conversion unit; a fourth capacitor element to which the signal is transferred by the third transfer unit; and a fourth transfer unit configured to transfer the signal from the fourth capacitor element to the input node.
10. The solid state imaging device according to claim 1 further comprising: a first substrate; and a second substrate electrically connected to the first substrate, wherein the first photoelectric conversion unit is formed on the first substrate, and the digital acquisition unit is formed on the second substrate.
11. The solid state imaging device according to claim 10, wherein the first transfer unit is formed on the second substrate.
12. The solid state imaging device according to claim 10, wherein the first transfer unit is formed on the first substrate.
13. The solid state imaging device according to claim 12, wherein the ramp wave generating unit is formed on the first substrate.
 14. The solid state imaging device according to claim further comprising a third substrate electrically connected to the second substrate, wherein the third substrate has a digital signal processing circuit configured to process the digital value acquired by the digital value acquisition unit.
 15. An imaging system comprising: a solid state imaging device including a first photoelectric conversion unit configured to generate a signal in accordance with an incident light by photoelectric conversion, a first transfer unit configured to transfer the signal from the first photoelectric conversion unit, a ramp wave generating unit that has an input node to which the signal is transferred and configured to generate a ramp wave whose voltage changes with time at a slope in accordance with a potential of the input node, a detection unit configured to detect a change in a relationship between a voltage of the ramp wave and a threshold voltage, a ramp wave reset unit configured to reset the voltage of the ramp wave when the detection unit detects a change in the relationship between the voltage of the ramp wave and the threshold voltage, a control unit configured to cause the detection unit to repeatedly detect a change in the relationship between the voltage of the ramp wave and the threshold voltage by repeating generation of the ramp wave by the ramp wave generating unit and the reset by the ramp wave reset unit within a predetermined period, and a digital value acquisition unit configured to acquire a digital value corresponding to the number of repetitions for which a change in the relationship between the voltage of the ramp wave and the threshold voltage is detected by the detection unit within the predetermined period; and an image processing unit configured to process an image signal output from the solid state imaging device..
